Alpha Level 2 Processor

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The Level 2 trigger decision is made by a set of 4 processor boards sitting in a single crate. The processor is a 500 MHz DEC Alpha chip and the board design is based on the DEC PC164 board design. The trigger data is sent to interface boards in the Level 2 crate. The interface boards send the data to the processor boards over a custom 128 bit wide "Magic Bus" on the J3 backplane. The processor boards use a custom PCI bridge implemented in a Xilinx FPGA to send the data to main memory. Another Xilinx FPGA is used to provide a bridge between the PCI bus and Magic Bus for bi-directional programmed I/O. A third Xilinx FPGA PCI device is used for communicating the trigger decision to the global trigger system. Tundra’s Universe chip is used to provide the PCI to VME interface which provides the path for inserting the trigger data in the DAQ data stream. The prototype Level 2 processor board is currently being built.

This work is supported by the University of Michigan and by the Department of Energy.
For problems or questions regarding this web contact myron@umich.edu.

Last updated: February 13, 2002.